38709 Experimental Training Board has been designed specifically for the study of Odd Parity Generator and Odd Parity Checker in solid state version. Odd Parity Generator and Odd Parity Checker play an important role in error detection. As Odd Parity Generator and Odd Parity Checker are now a days being used quite extensively in electronics, this Training Board has great educational value. 

Practical experience on these boards carries great educative value for Science and Engineering Students. 

Object

1. 12 bit odd parity generator
2. 13 bit odd parity checker

Features
The board consists of the following built-in parts:

1. Toggle Switches : 13 nos.
2. Led's : 15 (13 for input bits and 2 for output)
3. ICs : 7486/3 
4. Adequate no. of other electronic components.
5. Mains ON/OFF switch, Fuse and Jewel light.
6. The unit is operative on 230V at 50Hz AC Mains.
7. Strongly supported by detailed Operating Instructions, giving details of Object, Theory, Design procedures, Report Suggestions and Book References.

Technical specifications 

1. Data Width:
   1. Odd Parity Generator: 12 bits
   2. Odd Parity Checker: 13 bits
2. Parity Type:
   1. Odd Parity
3. Input Interface:
   1. Odd Parity Generator: 12-bit input data
   2. Odd Parity Checker: 13-bit input data (12 data bits + 1 parity bit)
4. Output Interface:
   1. Odd Parity Generator: Single-bit output indicating whether the received data from 12 bits has even parity.
   2. Odd Parity Checker: Single-bit output indicating whether the received data from 13 bits has even parity.
5. Logic Operation:
   1. Odd Parity Generator: XOR operation for generating the parity bit.
   2. Odd Parity Checker: XOR operation for checking the parity.
6. Implementation Technology:
   1. Digital logic gates – XOR gate.
7. Simplicity and Scalability:
   1. This design is for 12 bits only and it can be extended for 16, 32, 64, 128, 256 bits and more according to the bits size the number of Logic Gates required will also increase.
8. Specification of Logic Probe:
   1. Operating Voltage  : 5V regulated DC at 150mA , Ripple < 3mV
   2. Logic State Indications :
      1. High Level '1'  : 'H' (HIGH)
      2. Low Level '0'   : 'L'(LOW)
   3. Logic Families    : TTL
   4. Frequency    : Upto 50MHz for TTL